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1 ltc1642 1642fb hot swap controller the ltc ? 1642 is a 16-pin hot swap tm controller that allows a board to be safely inserted and removed from a live backplane. using an external n-channel pass transis- tor, the board supply voltage can be ramped up at an adjustable rate. a high side switch driver controls the n-channel gate for supply voltages above 2.97v. the sense pin allows foldback limiting of the load current, with circuit breaker action after an adjustable delay time. the delay allows the part to power-up in current limit. the crwbr output can be used to trigger an scr for crowbar protection of the load if the input supply exceeds an adjustable threshold. the reset output can generate a system reset with adjustable delay when the supply voltage falls below an adjustable threshold. the on pin cycles the board power. the ltc1642 is available in the 16-pin ssop package. adjustable undervoltage and overvoltage protection foldback current limit adjustable current limit time-out protected against surges to 33v single channel nfet driver latch off or automatic retry on current fault driver for scr crowbar on overvoltage adjustable reset timer reference output with uncommitted comparator 16-pin ssop package hot board insertion electronic circuit breaker infiniband tm systems 1n4705 18v 12v backplane (short pin) plug-in card v cc sense gate gnd brk tmr ltc1642 rst tmr on fault ov reset fb crwbr comp + comp C 0.33 f 0.33 f 2n2222 mcr 12dc ref 0.1 f 2.87k 1% 110k 1% 100 ? 5% 107k 1% 13k 1% fds6630a 0.01 f 0.047 f c load 12v at 2.5a 330 ? 5% 0.010 ? 5% 11.3k 1% power-good = 11.4v 1642 ta01 + compout gnd uv = 10.8v ov = 13.2v applicatio s u features typical applicatio u descriptio u , ltc and lt are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
2 ltc1642 1642fb supply voltage (v cc ) .................................C 0.3v to 33v sense pin ................................... C 0.3v to (v cc + 0.3v) on, fb, ov, comp + , comp C reset, fault, compout .....................C 0.3v to 18.5v operating temperature range ltc1642c ............................................... 0 c to 70 c ltc1642i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c the ltc1642a is recommended for applications where v cc is higher than 12v. absolute axi u rati gs w ww u package/order i for atio uu w (note 1) dc electrical characteristics symbol parameter conditions min typ max units v cc operating voltage range 2.97 16.5 v i cc v cc supply current on = v cc 1.25 3.0 ma v lkhi v cc undervoltage lockout v cc rising 2.55 2.73 2.95 v v lklo v cc undervoltage lockout v cc falling 2.35 2.50 2.95 v v lkhyst v cc undervoltage lockout hysteresis 230 mv v fb fb pin voltage threshold fb falling 1.208 1.220 1.232 v ? v fb fb pin threshold supply variation fb falling, 2.97v v cc 16.5v 515 mv v fbhst fb pin voltage threshold hysteresis 3 mv i fb(in) fb pin input current v ov = 5v 0 1 a v ov ov pin voltage threshold ov rising 1.208 1.220 1.232 v ? v ov ov pin threshold supply variation ov rising, 2.97v v cc 16.5v 515 mv v ovhyst ov pin voltage threshold hysteresis 3 mv i ov(in) ov pin input current v fb = 5v 0 1 a v rst rst tmr pin voltage threshold rst tmr rising 1.200 1.220 1.250 v ? v rst rst tmr pin threshold supply variation rst tmr rising, 2.97v v cc 16.5v 515 mv i rst rst tmr pin current timer on C 1.5 C 2.0 C 2.5 a timer off, v rsttmr = 1.5v 10 ma v brk brk tmr pin voltage threshold brk tmr rising 1.200 1.220 1.250 v ? v brk brk tmr pin threshold supply variation brk tmr rising, 2.97v v cc 16.5v 515 mv i brk brk tmr pin current timer on C15 C20 C30 a timer off, v brktmr = 1.5v 10 ma v cr crwbr pin voltage threshold crwbr rising 375 410 425 mv ? v cr crwbr pin threshold supply variation 2.97v v cc 16.5v 415 mv the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v unless otherwise specified. order part number consult ltc marketing for parts specified with wider operating temperature ranges. ltc1642cgn ltc1642ign order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 crwbr brk tmr rst tmr on reset fault fb gnd v cc sense gate ref comp C comp + compout ov gn package 16-lead plastic ssop t jmax = 150 c, ja = 130 c/w gn part marking 1642 1642i
3 ltc1642 1642fb i cr crwbr pin current crwbr on, v crwbr = 0v C30 C45 C60 a crwbr on, v crwbr = 2.1v C1000 C1500 a crwbr off, v crwbr = 1.5v 2.3 ma v cb circuit breaker trip voltage v cb = (v cc C v sense ), v fb = gnd 15 25 36 mv v cb = (v cc C v sense ), v fb = 1v 45 52.5 60 mv 2.97v v cc 16.5v, v cb = (v cc C v sense ), v fb = gnd 12 25 39 mv v cb = (v cc C v sense ), v fb = 1v 42 52.5 63 mv i sense sense pin input bias current v cc = v sense = 16.5v 0.5 a i gate gate pin output current charge pump on, v gate = gnd C20 C25 C30 a charge pump off, v gate = 5v 10 ma ? v gate external n-channel gate drive v gate C v cc, v cc = 2.97v 4.5 5.9 8.0 v v gate C v cc, v cc = 5v 10 11.5 14 v v gate C v cc, v cc = 15v 4.5 8.5 18 v v onhi on pin threshold on rising 1.30 1.34 1.38 v v onlo on pin threshold on falling 1.20 1.22 1.26 v v onhyst on pin hysteresis 110 mv i on(in) on pin input current v on = 5v 0 1 a v ol output low voltage reset, fault, compout i ol = 1.54ma 0.4 v reset, fault i o = 5ma 2 v i pu logic output pull-up current reset, fault = gnd C 15 a v ref reference output voltage no load 1.208 1.220 1.232 v ? v lnr reference supply variation 2.97v v cc 16.5v, no load 515 mv ? v ldr reference load regulation i o = 0ma to C1ma, sourcing only 2.5 7.5 mv i rsc reference short-circuit current v ref = 0v 4.5 ma v cos comparator offset voltage v cm = v ref 10 mv v chyst comparator hysteresis v cm = v ref 3mv dc electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v unless otherwise specified. symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. typical perfor a ce characteristics uw temperature ( c) C50 C25 0 25 50 75 100 125 ? v gate (v) 1642 g03 16 14 12 10 8 6 4 2 0 v cc = 12v v cc = 5v v cc = 15v v cc = 3v ? v gate vs temperature temperature ( c) C50 C25 0 25 50 75 100 125 i gate ( a) 1642 g04 30 29 28 27 26 25 24 23 22 21 20 v gate = 0v v cc = 3v v cc = 5v v cc = 12v v cc = 15v i gate vs temperature v cc (v) 3 6 9 12 15 ? v gate (v) 1642 g26 15 12 9 6 3 0 t a = 25 c ? v gate vs v cc
4 ltc1642 1642fb typical perfor a ce characteristics uw temperature ( c) C50 C25 0 25 50 75 100 125 fb threshold voltage (v) 1642 g06 1.226 1.224 1.222 1.220 1.218 1.216 1.214 v cc = 5v fb falling fb rising temperature ( c) C50 C25 0 25 50 75 100 125 ov threshold voltage (v) 1642 g07 1.226 1.224 1.222 1.220 1.218 1.216 1.214 v cc = 5v ov falling ov rising ov threshold voltage vs temperature fb threshold voltage vs temperature v cc (v) 3 6 9 12 15 crwbr driver current (ma) 1642 g35 2.0 1.6 1.2 0.8 0.4 0 t a = 25 c crwbr driver current vs v cc v cc (v) 3 6 9 12 15 fb threshold voltage (v) 1642 g27 1.232 1.228 1.224 1.220 1.216 1.212 1.208 fb rising fb falling t a = 25 c fb threshold voltage vs v cc ov threshold voltage vs v cc v cc (v) 3 6 9 12 15 ov threshold voltage (v) 1642 g28 1.232 1.228 1.224 1.220 1.216 1.212 1.208 ov rising ov falling t a = 25 c temperature ( c) C50 C25 0 25 50 75 100 125 crwbr driver current (ma) 1642 g13 1.45 1.44 1.43 1.42 1.41 1.40 1.39 1.38 v cc = 5v crwbr driver current vs temperature temperature ( c) C50 C25 0 25 50 75 100 125 crwbrCtmr threshold voltage (mv) 1642 g05 405 404 403 402 401 400 399 398 397 396 395 v cc = 5v crwbr-tmr threshold voltage vs temperature v cc (v) 3 6 9 12 15 i gate ( a) 1642 g23 25 20 15 10 5 0 v gate = 0v t a = 25 c i gate pull-up current vs v cc v gate (v) 04 8 12 16 20 24 i gate (a) 1642 g36 128 112 96 80 64 48 32 16 0 v cc = 12v t a = 25 c v cc = 3.3v v cc = 5v gate pull-down current (current limit active)
5 ltc1642 1642fb v cc (v) 02550 i cc (ma) 1642 g25 20 10 0 v on = 5v t a = 25 c v on = 0v typical perfor a ce characteristics uw i cc vs v cc on pin threshold voltage vs temperature temperature ( c) C50 C25 0 25 50 75 100 125 on pin threshold voltage (v) 1642 g22 1.40 1.36 1.32 1.28 1.24 1.20 v cc = 12v on rising on falling v cc (v) 3 6 9 12 15 v ref (v) 1642 g24 1.232 1.228 1.224 1.220 1.216 1.212 1.208 t a = 25 c v ref vs v cc v cc (v) 3 6 9 12 15 pull-up current ( a) 1642 g14 160 140 120 100 80 60 40 20 0 t a = C55 c t a = 125 c t a = 25 c temperature ( c) C50 C25 0 25 50 75 100 125 voltage (mv) 1642 g16 600 500 400 300 200 100 0 v cc = 12v v cc = 5v v cc = 15v v cc = 3v i ol = 1.54ma temperature ( c) C50 C25 0 25 50 75 100 125 voltage (v) 1642 g17 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v cc = 12v v cc = 5v v cc = 15v v cc = 3v i ol = 5ma temperature ( c) C50 C25 0 25 50 75 100 125 current limit threshold voltage (mv) 1642 g20 27.5 27.0 26.5 26.0 25.5 25.0 24.5 v cc = 3v fb = 0v v cc = 15v v cc = 12v v cc = 5v fault and reset pull-up current (i oh ) vs v cc fault and reset v ol vs temperature fault and reset v ol vs temperature current limit threshold voltage (full foldback) vs temperature current limit threshold voltage (nominal) vs temperature temperature ( c) C50 C25 0 25 50 75 100 125 current limit threshold voltage (mv) 1642 g21 57.0 56.5 56.0 55.5 55.0 54.5 54.0 53.5 v cc = 3v fb = 1v v cc = 15v v cc = 5v v cc = 12v reference o/p impedance i ref (ma) 0 2.5 5 7.5 10 12.5 15 17.5 20 ? v ref (mv) 1642 g37 0 C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 C22 C42 v cc = 12v, 15v t a = 25 c v cc = 5v v cc = 3.3v
6 ltc1642 1642fb pi fu ctio s uuu crwbr (pin 1): overvoltage crowbar circuit timer and trigger. this pin controls an external overvoltage crowbar circuit. a capacitor from the pin to ground sets a 9ms/ f delay after an overvoltage occurs until an external scr is triggered. see applications information. ground the crwbr pin if unused. brk tmr (pin 2): circuit breaker timer. connect a capacitor from brk tmr to ground to set a 60ms/ f delay from the time the sense resistor current reaches its limit until the fet is shut off. fault output is then asserted and the fet remains off until the chip is reset. ground brk tmr to allow the part to remain in current limit indefinitely. rst tmr (pin 3): analog system/reset timer. a capaci- tor from this pin to ground sets a 0.6s/ f delay from the on pin going high to the start of the gate pins ramp. it also sets the delay from output voltage good, as sensed by the fb pin, to reset going high. on (pin 4): on control input. when on is low the gate pin is grounded and fault goes high. the gate pin voltage starts ramping up one rst tmr timing cycle after on goes high. pulsing the on pin low for at least 2 s resets the chip if it latches off after a sustained overvoltage or current limit. the threshold for a low to high transition is 1.34v with 110mv of hysteresis. a 21v zener clamp limits the voltage at this pin. the pin can be safely tied to v cc > 21v through a series resistor that limits the current below 1ma. reset (pin 5): open drain reset output. reset is pulled low if the voltage at the fb pin is below its trip point. reset goes high one reset timing cycle after the fb voltage exceeds its trip point plus 3mv of hysteresis. reset has a weak pull-up to one diode drop below v cc and an external resistor can pull the pin above v cc . a 21v zener clamp limits the voltage at this pin. the pin can be safely tied to v cc > 21v through a series resistor that limits the current below 1ma. fault (pin 6): open drain fault output. fault is pulled low when the part turns off following a sustained overvolt- age or current limit. it goes high 2 s after the on pin goes low. fault has a weak pull-up to one diode drop below v cc and an external resistor can pull the pin above v cc . a 21v zener clamp limits the voltage at this pin. the pin can be safely tied to v cc > 21v through a series resistor that limits the current below 1ma. fb (pin 7): output voltage monitor and foldback input. the fb comparator can be used with an external resistive divider to monitor the output supply voltage. when the fb voltage is lower than 1.22v the reset pin is pulled low. reset goes high one system timing cycle after the voltage at fb exceeds its threshold by 3mv of hysteresis. a low pass filter at the comparators output prevents negative voltage glitches from triggering a false reset. gnd (pin 8): chip ground.
7 ltc1642 1642fb ov (pin 9): overvoltage input. when the voltage on ov exceeds its trip point the gate pin is pulled low immedi- ately and the crwbr timer starts. if ov remains above its trip point (minus 3mv of hysteresis) long enough for crwbr to reach its trip point, then the part turns off until reset by pulsing the on pin low. otherwise, the gate pin begins ramping up one rst tmr timing cycle after ov goes below its trip point. ground the ov pin to disable overvoltage protection. compout (pin 10): uncommitted comparators open drain output. comp + (pin 11): uncommitted comparators noninvert- ing input. comp (pin 12): uncommitted comparators inverting input. ref (pin 13): reference voltage output. the 1.22v 1% reference should be bypassed with a 0.1 f compensation capacitor. for v cc = 5v it can source 1ma. gate (pin 14): gate drive for the external n-channel mosfet. an internal charge pump provides at least 4.5v of gate drive and sources 25 a. the pin requires an external series rc network to ground to compensate the current limit loop and to limit the ramp rate. a resistor of 100 ? is also recommended in series with the mosfet pi fu ctio s uuu gate to suppress high frequency oscillations. gate is immediately pulled to ground when the overvoltage com- parator trips or the input supply is below the undervoltage lockout trip point. during current limit the gate voltage is adjusted to maintain constant load current until the circuit breaker timer trips. at that point gate is pulled to ground until the chip is reset. clamp the gate pin with an 18v zener diode (in4705) to ground if the supply is 8v or higher. sense (pin 15): current sense input. to use the current limit place a sense resistor in the supply path between v cc and sense. when the drop across the resistor exceeds a threshold voltage, the gate pin is adjusted to maintain a constant load current and the circuit breaker timer is started. a foldback feature reduces the current limit as the voltage at fb approaches ground. short sense to v cc to disable the current limiting. v cc (pin 16): positive supply voltage. an internal under- voltage lockout circuit holds the gate pin at ground until v cc exceeds 2.73v. if v cc exceeds 16.5v an internal shunt regulator protects the chip from v cc and sense pin voltages up to 33v. in this case the gate pin voltage will usually be low but this is not guaranteed; use the ov pin to ensure that the pass device is off. the v cc pin also provides a high side connection to the sense resistor.
8 ltc1642 1642fb + C 7 fb 1.22v 0.41v 1.22v + C 16 v cc 14 gate charge pump 25 a 23mv to 53mv C + 9 ov 1.22v C + 4 on 1.22v C + v cc v cc 2.7v C + 11 12 comp C comp + rising delay 15 s to 100 s rising delay 15 s to 100 s rising delay 2 s rising delay 10 s 1 crwbr 45 a 1.5ma 1.22v 2 brk tmr 20 a 1.22v 3 rst tmr 1642 bd 2 a 6 fault 10 a at 5v v cc 15 C + C + sense + C 5 reset 10 a at 5v v cc 13 ref logic C + C + 10 compout 21v 21v 21v 21v 21v 21v 21v 21v 21v 21v 21v 21v 21v block diagra w
9 ltc1642 1642fb applicatio s i for atio wu u u hot circuit insertion when a circuit board is inserted into a live backplane its supply bypass capacitors can draw large currents from the backplane power bus as they charge. these currents can permanently damage connector pins and can glitch the backplane supply, resetting other boards in the system. the ltc1642 limits the charging currents drawn by a boards capacitors, allowing safe insertion into a live backplane. in the circuit shown in figure 1 the ltc1642 and the external nmos pass transistor q1 work together to limit charging currents. waveforms at board insertion are shown in figure 2. when power is first applied to v cc the chip holds q1s gate at ground. after an adjustable delay a 25 a current source begins to charge the external capacitor c2, so choose c2 to limit the inrush current i inrush charging the boards bypass capacitance c load according to the equation: c2 c ? 25 a i load inrush = an internal charge pump supplies the 25 a gate current, ensuring sufficient gate drive to q1. at 3v v cc the minimum gate drive is 4.5v; at 5v v cc the minimum is 10v; at 15v v cc the minimum is again 4.5v, due to an internal zener clamp from the gate pin to ground. resistor r3 limits this zeners transient current during board insertion and removal and protects against high frequency oscillations in q1. d1 provides additional protection against supply spikes. the delay before the gate pin voltage begins ramping is determined by the system timer. it comprises an external capacitor c1 from the rst tmr pin to ground; an internal 2 a current source feeding rst tmr from v cc ; an internal comparator, with the noninverting input tied to rst tmr and the inverting input tied to the 1.22v reference; and an internal nmos pull-down. in standby, the nmos holds rst tmr at ground. when the timer starts the nmos turns off and the rst tmr voltage ramps up as the current source charges the capacitor. when rst tmr reaches 1.22v the timer comparator trips, the gate voltage begins ramping up and rst tmr returns to ground. the timer delay is: t rsttmr = (615ms/ f) c1. the second rst tmr cycle indicates that v out is within tolerance; it is discussed in the undervoltage monitor section. gate on 14 sense 15 fault 6 4 brk tmr 2 v cc 16 r2 0.010 ? q1 fds6630a gnd ltc1642 8 rst tmr 3 1642 f01 r3 100 ? r4 330 ? d1 1n4705 18v c2 0.047 f c load + c1 0.33 f c4 0.33 f all resistors 5% unless noted reset delay = 200ms short-circuit duration = 10ms v in 12v 2.5a v out r7 24k r10 30k figure 1. supply control circuitry powering-up in current limit ramping the gate pin voltage limits the current to i = 25 a ? c load /c2, where c2 is the external capacitor connected to the gate and c load is the load capacitance. if the value of c load is uncertain, then a worst-case design can often result in needlessly long ramp times, and it may be better to limit the charging current by powering up in current limit. current limiting and solid-state circuit breaker the current can be limited by connecting a sense resistor between the ltc1642s v cc and sense pins. when the voltage drop across this resistor reaches a limiting value, figure 2. timing at board insertion 100ms/div 1642 f02 ov 10v/div rst tmr 2v/div gate 20v/div v out 20v/div
10 ltc1642 1642fb applicatio s i for atio wu u u an internal servo loop adjusts the gate pin voltage such that q1 acts as a constant current source. the voltage limit across r2 increases as the output charges; this foldback in the current limit helps to even out q1s power dissipa- tion. the output is sensed at the fb pin. when fb is grounded, the sense voltage is limited to 26mv. when fb is greater than 0.7v, the limit is 56mv and the full depen- dence is shown in figure 3. when the sense resistor voltage is 3mv below its limit, the circuit breaker timer starts. once brk tmr reaches its threshold, the circuit breaker opens, the gate pin is pulled to ground (cutting off q1) and fault is asserted. the parameter v cb specified in the dc electrical character- istics refers to the voltage difference between the v cc and sense pins needed to start the circuit breaker timer. the limiting value maintained by the servo loop is 3mv higher than v cb . should the sense resistor voltage drop below its limit before the timer trips, the gate voltage begins ramping back up immediately and the brk tmr pin returns to ground. however, due to the slow gate ramp, q1 continues to dissipate substantial power for some time. connecting r10 in series with timing capacitor c4 (as shown in figure 1) ensures that the circuit breaker trips in the event of repetitive, but brief, load shorts. the delay before the circuit breaker opens is: t brktmr = c4 (61k ? C r10). once the circuit breaker trips, gate and fault remain at ground until the chip is restarted. to restart, hold the on pin low for at least 2 s and fault will go high. then take on high again and the gate will ramp up after a system timing cycle. or, configure the ltc1642 to restart itself after the circuit breaker trips by connecting fault to the on pin, as shown in the next section. the servo loop controlling q1 during current limit has a unity-gain frequency of about 125khz. in figure 1, r4 and c2 provide compensation. to ensure stability the product 1/(2 ? ? r4 ? c2) should be kept below the unity-gain frequency, and c2 should be more than q1s input capaci- tance c iss . a good starting point for c2 is 0.047 f and r4 is 330 ? . keep r4 100 ? . typical waveforms during a load short to ground are shown in figure 4. the load is shorted to ground at time 1. the gate voltage drops until the load current equals its maximum limit, and the circuit breaker timer starts. the short is cleared at time 2, before the timer trips. the brk tmr pin returns to ground, and the gate voltage begins ramping up. at time 3 the load is shorted again and at time 4 the timer trips, pulling the gate to ground and asserting fault. although the short is cleared at time 5, fault doesnt go high until the on pin is pulled low at time 6. at time 7 on goes high and the system timer starts. when it trips at time 8 the gate voltage begins ramping. to disable current limit and electronic circuit breaker protection, tie the sense pin to v cc , the brk tmr pin to gnd and omit compensating resistor r4. fb pin voltage (mv) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 maximum sense resistor voltage (mv) 1642 f03 70 60 50 40 30 20 10 0 figure 3. foldback current limit figure 4. current limit and circuit breaker timing 40ms/div 1642 f04 t 1 t 2 t 3 t 4 t 5 t 7 t 6 t 8 rst tmr 2v/div on 20v/div fault 20v/div brk tmr 2v/div v out 20v/div gate 20v/div i load 5a/div
11 ltc1642 1642fb applicatio s i for atio wu u u automatic restart after the circuit breaker opens the ltc1642 will automatically attempt to restart itself after the circuit breaker opens if the fault output is tied to the on pin. the circuit is shown in figure 5. diode d1 blocks the weak fault pull-up current source from unbal- ancing the r6-r5 divider. during a continuous current limit such as a load short, q1s duty cycle is equal to the circuit breaker timer period, divided by the sum of the circuit breaker and system timer periods: short - circuit duty cycle = + c cc 4 410 1 ? the duty cycle is 9% for the figure 5 circuit. waveforms during a load short are shown in figure 6. undervoltage lockout an internal undervoltage lockout circuit holds the charge pump off until v cc exceeds 2.73v. if v cc falls below 2.5v, it turns off the charge pump and clears overvoltage and current limit faults. for higher lockout thresholds tie the on pin to a resistor divider driven from v cc , as shown in figure 7. this circuit keeps the charge pump off until v cc exceeds (1+r6/r5) ? 1.34v, and also turns it off if v cc falls below (1+r6/r5) ? 1.22v. d1 1n4148 d2 1n4705 18v gate on 14 sense 15 4 fault 6 brk tmr 2 v cc 16 r2 0.015 ? q1 fds6630a gnd ltc1642 8 rst tmr 3 r5 60.4k 1% r6 464k 1% r10 30k 1642 f05 r3 100 ? r4 330 ? c2 0.047 f + c1 0.33 f c4 0.33 f all resistors 5% unless noted v in 12v 2.5a v out c load figure 5. automatic restart circuit figure 6. automatic retry following a load short v gate 20v/div v out 10v/div v brktmr 1v/div v rsttmr 1v/div 40ms/div 1642 f06 d1 1n4705 18v gate 14 sense 15 on 4 v cc 16 r2 0.015 ? q1 fds6630a gnd ltc1642 8 rst tmr 3 r6 464k 1% r5 60.4k 1% v in 12v 2.5a 1642 f07 r3 100 ? r4 330 ? c2 0.047 f + c1 0.33 f all resistors 5% unless noted v out undervoltage lockout threshold = 10.7v c load figure 7. setting a higher undervoltage lockout
12 ltc1642 1642fb overvoltage protection the ltc1642 can protect a load from overvoltages by turning off the pass transistor if the supply voltage ex- ceeds an adjustable limit, and by triggering a crowbar scr if the overvoltage lasts longer than an adjustable time. the part can also be configured to automatically restart when the overvoltage clears. the overvoltage protection circuitry is shown in figure 8. the external components comprise a resistor divider driving the ov pin, timing capacitor c5, npn emitter follower q2, and crowbar scr q3. because the mcr12dc is not a sensitive-gate device, the optional resistor shunt- ing the scr gate to ground is omitted. the internal components comprise a comparator, 1.22v bandgap ref- erence, two current sources, and a timer at the crwbr pin. when v cc exceeds (1+r6/r5) ? 1.22v the comparators output goes high and internal logic turns off q1 and starts the timer. this timer has a 0.410v threshold and uses the crwbr pin; when crwbr reaches 0.410v the timer comparator trips, and the current sourced from v cc in- creases to 1.5ma. emitter follower q2 boosts this current to trigger crowbar scr q3. the ramp time ? t needed to trip the comparator is: t crwbr = 9.1(ms/ f) c5 d1 1n4705 18v gate on 14 sense 15 crwbr 1 4 fault 6 ov 9 v cc 16 r2 0.015 ? q1 fds6630a gnd ltc1642 8 rst tmr 3 r6 127k 1% r5 12.4k 1% v in 12v 2.5a 1642 f08 r3 100 ? r4 330 ? c2 0.047 f + c1 0.33 f all resistors 5% unless noted ov comparator trips at v in = 13.85v reset time = 200ms crowbar delay time = 90 s q2 2n2222 q3 mcr12dc * add 220 ? resistor if using a sensitive-gate scr c5 0.01 f v out c load figure 8. overvoltage protection circuitry figure 9. overvoltage timing (input side) applicatio s i for atio wu u u 100ms/div 1642 f09 in ov gate out crwbr rst tmr on fault 20v/div 2v/div 50v/div 20v/div 1v/div 2v/div 20v/div 20v/div t 1 t 2 t 3 t 4 t 5 t 7 t 6 t 8 once the crwbr timer trips the ltc1642 latches off: after the overvoltage clears gate and fault remain at ground and crwbr continues sourcing 1.5ma. to restart the part after the overvoltage clears, hold the on pin low for at least 2 s and then bring it high. the gate voltage will begin ramping up one system timing cycle later. the part will restart itself if fault and on are connected. figure 9 shows typical waveforms when the divider is driven from v cc . the ov comparator goes high at time 1, causing the chip to pull the gate pin to ground and start the crwbr timer. at time 2, before the timers compara- tor trips, ov falls below its threshold; the timer resets and gate begins charging one system timing cycle later at time 3. another overvoltage begins at time 4, and at time 5 the crwbr timer trips; fault goes low and the crwbr pin begins sourcing 1.5ma. even after ov falls below 1.22v at time 6, gate and fault stay low, and crwbr continues to source 1.5ma. fault goes high when on goes low at time 7, and gate begins charging at time 8, one rst tmr cycle after fault goes high. figure 10 shows typical waveforms when the ov divider is driven from the n-channels output side. because the voltage driving the divider collapses after the ov compara- tor trips, fault stays high and crwbr stays near ground, which prevents the pin from triggering an scr. the gate voltage begins ramping up after a rst tmr timing cycle. to disable overvoltage protection completely, tie the ov and crwbr pins to gnd. for overvoltage protection at the gate pin, but without latch off or a crowbar scr such as q3 in figure 1, tie crwbr to gnd.
13 ltc1642 1642fb the pull-up voltage on the reset and fault pins follows v cc until the shunt regulator turns on. when the regulator is on the pull-up voltage is 14.4v. undervoltage monitor the ltc1642 will assert reset if a monitored voltage falls below an adjustable minimum. when the monitored volt- age has exceeded its minimum for at least one system timing cycle, reset goes high. the monitoring circuitry comprises an internal 1.22v bandgap reference, an inter- nal precision voltage comparator and an external resistive divider to monitor the output supply voltage. the circuit is shown in figure 12, and typical waveforms in figure 13. when the voltage at the fb pin rises above its reset threshold (1.22v), the comparator output goes low and a timing cycle starts (times 1 and 5). following the cycle reset is pulled high. at time 2 the voltage at fb drops below the comparators threshold and reset is pulled low. if the fb pin rises above the reset threshold for less than a timing cycle the reset output will remain low (time 3 to time 4). the 15 a pull-up current source to v cc on reset has a series diode so the pin can be pulled above v cc by an external pull-up resistor without forcing current back into the supply. automatic restart if there is an overvoltage, and the resistor divider feeding ov is connected to the output of the n-channel pass transistor, the ltc1642 will automatically restart even if fault is not tied to on. if the divider is connected to the input side, the ltc1642 will restart itself only if fault is tied to on, and only after the overvoltage clears. the ov and fb comparators the propagation delay through the ov and fb compara- tors on low to high transitions depends strongly on the differential input voltage. the relationship is shown in figure 11. the minimum propagation delay for large overdrives is about 20 s. in addition the comparators have 3mv of hysteresis. internal voltage clamp protection the ltc1642 includes a shunt regulator to protect itself from v cc and sense pin voltages up to 33v. the regulator turns on when v cc exceeds 16.5v and limits most of the chips circuitry to 15v. when it is on the chip functions normally with one exception: if the charge pump is on, the gate voltage is usually near ground but this is not guaranteed. use the ov pin to ensure that gate is grounded. applicatio s i for atio wu u u figure 10. overvoltage timing (output side) ov overdrive (mv) 0 40 80 120 160 200 240 ov comparator propagation delay ( s) 1642 f11 70 60 50 40 30 20 10 0 figure 11. ov comparator propagation delay vs overdrive voltage 100ms/div 1642 f10 in ov gate out crwbr rst tmr fault 20v/div 2v/div 20v/div 20v/div 2v/div 2v/div 20v/div
14 ltc1642 1642fb applicatio s i for atio wu u u the undervoltage monitor behaves differently if fb is above its threshold when the gate begins ramping: reset goes high as soon as the gate ramp begins. reset goes low immediately if v cc falls below the chips 2.5v internal undervoltage lockout threshold. to disable the undervoltage monitor, tie fb to ref and ground reset. d1 1n4705 18v gate on 14 sense 15 fb 7 reset 5 4 v cc 16 r2 0.015 ? q1 fds6630a gnd ltc1642 8 rst tmr 3 1642 f12 r3 100 ? r4 330 ? c2 0.047 f r9 95.3k 1% r8 12.4k 1% + c1 0.33 f all resistors 5% unless noted. fb comparator trips at v out = 10.7v v in 12v 2.5a v out c load figure 12. undervoltage monitoring circuitry figure 13. supply monitor waveforms reference current 100 a 1ma 10ma minimum ref compensation ( f) 1642 f14 0.1 0.2 0.4 1.0 2.0 4.0 10.0 figure 14. minimum ref compensation vs ref current reference the ltc1642s internal voltage reference is buffered and brought out to the ref pin. the buffer amplifier should be compensated with a capacitor connected between ref and ground. if no dc current is drawn from ref, 0.1 f ensures an adequate phase margin, but the minimum compensation increases if ref sources a substantial dc current, as shown in figure 14. t 1 t 2 t 3 t 4 t 5 250ms/div 1642 f09 v in 20v/div v rsttmr 1v/div v reset 10v/div
15 ltc1642 1642fb uncommitted comparator the uncommitted comparator has an open drain output. the comparator has 3mv of hysteresis: the output goes high when the differential input voltage exceeds 1.5mv and goes low when the differential input is less than C1.5mv. the comparators input transistors are mosfets so the input bias and offset currents are very small: typically picoamps at 25 c, increasing to nanoamps at 90 c. if the auxiliary comparator is unused, the comp + , comp C and compout pins may be left floating. applicatio s i for atio wu u u r6 sense resistor, r2 to short v cc pin r2 1642 f15 r5 v cc sense on gnd lt1642 i load i load figure 15. recommended layout for r1, r2 and r5 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. layout considerations one ounce copper exhibits a sheet resistance of 530 ? per square. to minimize self-heating, traces should be at least 0.02" wide per ampere of current and 0.03" is recommended. in high current applications, the voltage drop along traces can be appreciable. connect the ltc1642s v cc and sense pins directly across sense resistor r2 to prevent the power traces resistance from adding to r2. it is also a good practice to keep the resistor divider to the on pin close to the chip and the dividers connections to the v cc and gnd pins short. figure 15 shows an example layout.
16 ltc1642 1642fb ? linear technology corporation 1999 lt/lt 0805 rev b ? printed in usa related parts part number description comments ltc1421 hot swap controller two supplies from 3v to 12v and C12v ltc4211 hot swap controller with multifunction current control single supply from 2.5v to 16.5v, msop package lt4250 negative voltage hot swap controller in so-8 C 48v supplies, active current limit ltc1643 pci-bus hot swap controller 3.3v, 5v, 12v supplies for pci bus, active current limit typical applicatio u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com 12v hot swap circuit for infiniband modules d2 1n4705 18v ref comp C crwbr rst tmr brk tmr gnd v cc sense gate compout reset fb fault on ov comp + ltc1642 13 12 1 3 2 8 16 15 14 10 5 7 6 4 9 11 r3 100 ? c2 0.047 f r4 330 ? 5% r12 84.5k 1% r6 127k 1% r5 10.2k 1% r2 q1 c7 0.01 f r11 12.4k 1% c6 0.1 f c5 0.01 f c1* 0.033 f 30k c4 0.033 f d1* 1n4148 10k r9 681k 1% r8 100k 1% dc/dc converter input to converter's run/ss to dc/dc return 1642 ta02 vb_in vbxen_l vb_ret infiniband backplane infiniband module local power enable uv *install d1 for automatic restart if using d1, increase c1 start-up delay is 20ms typical circuit-breaker delay is 1ms typical ? fairchild (408) 822-2126 r e w o p e l u d o m2 r1 q w 5 2% 5 , ? 5 1 0 . 02 ? 1 6 6 s d f w 0 5% 5 , ? 7 0 0 . 00 ? 8 6 6 s d f long short long package descriptio u gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641)

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